Signaltap built-in logic analyzer usage record

Signaltap built-in logic analyzer usage record

0.Signal Tap II logic analyzer

The Signal Tap II (STP) logic analyzer is an FPGA built-in logic analyzer provided by Altera, which can monitor the internal signals of the FPGA within a certain range. The logic analyzer is written into the FPGA along with the RTL code, and the signal changes can be viewed in the software inherited by quartus. The logic analyzer is used in the following scenarios:

  • When there is no logic analyzer
  • When you need to observe the on-chip registers
  • The time window to observe is not long

The logic analyzer is not suitable for the following scenarios:

  • Observe the multi-bit signal for a long time (the capacity is insufficient and cannot be synthesized): In this case, it is recommended to use simulation software such as VCS to simulate
  • Observe port signals for a long time and have a logic analyzer: use the logic analyzer directly

1. Build STP logic analyzer

This logic logic analyzer uses file management, just select it in File-> .NewSignalTap II Logic Analysis File


After clicking, the STP interface as shown below will pop up


In subsequent operations, double-click the .stpfile in the file selection area of ​​Quartus to enter this interface.

2. Set up the STP logic analyzer

2.1. Set the signal to be observed

It should be noted that the design needs to be synthesized before this step, so that stp can read what signals are in the design. Then add signals as shown in the figure below:


After the addition is complete, it will look like this:


2.2. Set other information

The information to be set includes sampling clock, sampling depth and trigger signal, among which:

  • Sampling clock: indicates the clock used by the sampling system, and the design clock can be used
  • Sampling depth: the length of the sampling time window, that is, "how long is the data sampled", the longer the sampling window consumes more RAM resources, too large sampling depth will easily lead to integration failure due to insufficient RAM
  • Trigger signal and trigger mode: when to start sampling

Set the sampling clock and sampling depth as shown in the figure below:


Set the trigger signal as follows:


2.3. Select the hardware device

Then you need to select the debugger, connect the FPGA, debugger and PC, and perform the following operations in the following window (at the upper right of the overall window).


3. Re-integrate and download

Re-synthesize in the Quartus interface and perform programming. It should be noted that because STP is a hardware logic analyzer, in addition to replacing the hardware debugger (2.3), any changes to the above information need to be re-synthesized and deployed.

4. Observe the signal

Click the button shown in the figure below to observe the signal


If the button is gray, it may be due to:

  • No comprehensive deployment after modification
  • The FPGA is not connected to the PC through the debugger

If it is not for the above reasons, you can perform step 2.3 to refresh. After pressing the above button, the logic analyzer waits for the trigger signal, and then starts to record the specified signal after the trigger, as shown in the figure below:


In the waveform interface, you can click the left button to zoom in the waveform, and click the right button to zoom out.

Reference: Signaltap built-in logic analyzer usage record-Cloud + Community-Tencent Cloud