IO Constraints in FPGA Timing Constraint Theory

IO Constraints in FPGA Timing Constraint Theory

I/O constraints

  I/O constraints are mandatory constraints, including pin constraints and delay constraints.

Pin constraints

  The pin constraint refers to the pin assignment. We need to specify the values ​​of the PACKAGE_PIN and IOSTANDARD attributes of the pin. The former specifies the location of the pin, and the latter specifies the level standard corresponding to the pin.

  In vivado, use the following method to constrain the pins in xdc.

set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVCMOS18} [get_ports "led[0]"]

  Vivado stipulates that the pin level must be specified, otherwise an error will occur when the bit stream is generated in the last step.

  In addition to the pin position and level, there is also termination that is easy to overlook but can easily cause errors. When we use differential level, such as LVDS, when we use V6 IBUFDSto process the input differential signal, we can specify the terminal. Connect to TRUE.

   IBUFDS #(
      .DIFF_TERM("TRUE"),//Differential Termination
      .IOSTANDARD("DEFAULT")//Specify the input I/O standard
   ) IBUFDS_inst (
      .O(O),//Buffer output
      .I(I),//Diff_p buffer input (connect directly to top-level port)
      .IB(IB)//Diff_n buffer input (connect directly to top-level port)
   );

But in IBUFDS in Ultrascale, the option of termination is removed

   IBUFDS #(
      .DQS_BIAS("FALSE")//(FALSE, TRUE)
   )
   IBUFDS_inst (
      .O(O),//1-bit output: Buffer output
      .I(I),//1-bit input: Diff_p buffer input (connect directly to top-level port)
      .IB(IB)//1-bit input: Diff_n buffer input (connect directly to top-level port)
   );

We must manually specify it in the xdc or I/O Pors interface, otherwise an error may occur.

The author has taken a pit before, the differential port input, when the continuous input data is 11101111, the middle 0 cannot be pulled down, but it is still 1, and it will also happen at 000010000, which will lead to data transmission errors, and I found out later The termination is forgotten to add. Because the termination will affect the actual level of the signal, it will lead to FPGA judgment errors.

  When the synthesis is completed, we can click DRC to check the design rules. This step can report some key issues, such as the clock port is not assigned to the clock pin.

Delay constraint

  The delay constraint uses set_input_delayand set_output_delay, which are used for input and output respectively. The clock source can be a clock input pin or a virtual clock. But it should be noted that these two constraints do not play a role in delay . The specific reasons are analyzed below.

  • set_input_delay

  This constraint is the OFFSET=INsame as the function in ISE , but the setting method is different. The following figure shows the constraint illustration of input delay.

It is easy to understand from the figure,

T_inputdelay = Tco + TD

When the timing in the figure is met, the maximum delay is 2ns, and the minimum delay is 1ns.

Therefore, the timing constraints that need to be added are:

create_clock -name sysclk -period 10 [get_ports clkin]
set_input_delay 2 -max -clock sysclk [get_ports Datain]
set_input_delay 1 -min -clock sysclk [get_ports Datain]
  • set_output_delay

  The usage of set_output_delay is very similar to set_input_delay, so I won't go into it here. In the description of set_input_delay we mentioned above, you can see that this constraint tells vivado the delay relationship between our input signal and the input clock. The clock cycle constraint described below is the same principle, let vivado go on this premise. and Route. It is not about adjusting the delay of the input signal , because many FPGA engineers around me thought it was a constraint of adjusting the delay before they used this constraint instruction.

  If you want to adjust the delay of the input signal, you can only use IDELAY. In V6, the IDELAY module has 32 tap values, and each tap can delay 78ps, so the total is almost 2.5ns.

Reference: https://cloud.tencent.com/developer/article/1653045 FPGA Timing Constraint Theory: IO Constraints-Cloud + Community-Tencent Cloud