In the development of ISE, it is very convenient to generate the instantiation template of the HDL file, but in vivado, many students did not find this function, in fact, there are still functions, but many functions in vivado can be realized through tcl scripts, so Xilinx removed these functions from the graphics. Let's see how to generate HDL instantiation templates in vivado.
Design Utilities, click on the
Tools->Xilinx Tck Storeoption, as shown in Figure 1 below.
Design Utilities, as shown in Figure 2 below.
You don’t need to install it when you generate the instantiation template later, just go to the following steps.
Open Elaborated Design, as shown in Figure 3 below.
Tcl Consolethe execution
xilinx::designutils::write_template -template -verilogof instructions, can be seen as shown below 4. The prompt content, to find the corresponding position of the embodiment to generate the template file.
If you did not perform step 3, the following situation will occur
It can be seen that a Warning is prompted, and a .v file without a name is generated. If you open the file, you will find that there is no useful content in the file.
Well, at this point, the HDL instantiation template has been correctly generated. However, it is still a little troublesome to input the tcl command every time. We can set a tcl button to generate it with one click. The operation is as follows:
Tools->Custom Commands->Customize Commands, as shown in Figure 6 below.
After entering, follow the steps in the figure below to generate tcl instructions.
After the operation, you can see the tcl button logo in the menu bar of vivado, as shown in Figure 8 below.
In the future, the step of typing instructions can be replaced by clicking the button directly.
OK, the above is all the steps. But the instantiation templates generated in this way are sorted according to the interface type, the front is
input, the middle is
output, and the last is
inout, not according to our original port sorting, which may cause a little inconvenience.