Vivado auxiliary tool for FPGA timing constraints

Vivado auxiliary tool for FPGA timing constraints

Timing Constraint Assistant Tool

  What we talked about above is the xdc file method for timing constraints. Vivado also provides two graphical interface methods to help us with timing constraints: Edit Timing Constraints and Constraints Wizard. Both can be opened in Design after synthesis or implementation.

1. Timing Constraint Editor

  After opening it, all the constraints we have done before can be displayed. Of course, you can also add, delete or modify timing constraints.

  For example, if we want to add a new master clock, first select the one on the left Create Clock, and then click the +number to add constraints, and then you will see the following interface, follow the steps in the figure.

Among them, selecting the clock button will pop up a new window, as shown in the figure below, we only need to search and select based on the name of the clock.

2. Timing Constraint Wizard

  The timing constraint wizard can automatically identify the unconstrained master clock. We commented out the clock constraint for clk2 in the xdc file of the wave_gen project. After re-synthesis and implementation, open the timing constraint wizard, you can see that clk2 is detected as unconstrained. Click the edit button to complete the constraint after setting the parameters.

  The Timing Constraint Wizard will guide the designer to create constraints in the order of master clock constraints, derived clock constraints, input delay constraints, output delay constraints, timing exception constraints, asynchronous clock constraints, etc.

Reference: https://cloud.tencent.com/developer/article/1653057 Vivado Auxiliary Tool for FPGA Timing Constraints-Cloud + Community-Tencent Cloud