Pseudo path constraint of FPGA timing constraint actual combat

Pseudo path constraint of FPGA timing constraint actual combat

Pseudo path constraint

  In the section "2 Constraining the Master Clock" in this chapter, we see that when timing constraints are not added, the Timing Report will prompt a lot of errors, including cross-clock domain errors. We can directly right-click on it and set False path of two clocks.

This will automatically generate the following constraints in xdc:

set_false_path -from [get_clocks -of_objects [get_pins clk_gen_i0/clk_core_i0/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins clk_gen_i0/clk_core_i0/inst/mmcm_OUT1]

  In fact, these two clocks have already been created by the generated command before, so there is no need to repeat the long string of get_pins, so we can manually add the pseudo paths of these two clocks as follows:

set_false_path -from [get_clocks clk_rx] -to [get_clocks clk_tx]

The setting of the pseudo path is one-way. If the two clocks directly transmit data between each other, you also need to add the path from clk_txto clk_rx. In this project, there is only data transmission from rx to tx, so this one is fine.

  In the pseudo-path section, we mentioned that asynchronous reset also needs to add a pseudo-path. rst_pinThe reset input is used as an asynchronous reset in this project, so one more sentence needs to be added:

set_false_path -from [get_ports rst_pin]

  For clk_sampsum clk2, there is data exchange between them, but we have already restricted it before asynchronous, so there is no need to repeat the restriction here.

  There is a point to be reminded here. After the above constraints are added, the warning of the xdc file will be prompted during synthesis.

But this may be due to Vivado's synthesis process. When the constraint file was read, all the internal circuits were not built, and there was a clk_gen_i0/clk_core_i0/inst/mmcm_adv_inst/CLKIN1situation where no waiting ports were found . There are the following proofs:

  1. If the xdc file is set to be used only in Implementation, the warning will not be prompted
  2. After the implementation is completed, whether it is Timing Report or through tcl report_clocksinstructions, you can see that these clocks have been correctly constrained. The following figure shows the Timing Report after setting the above constraints.
Reference: FPGA Timing Constraint Practical Chapter of Pseudo Path Constraint-Cloud + Community-Tencent Cloud