The AXI bus consists of 5 channels:
Read address channel
Master -> Slave
Read data channel (including data channel and read response channel)
Slave -> Host
Write address channel
Master -> Slave
Write data channel (including data channel and valid signal of write data with one byte per 8bit)
Master -> Slave
Write response channel
Slave -> Host
The channel of the read operation is shown in the figure below
The channel of write operation is shown in the figure below
Common standard AXI systems are shown in the figure below, which usually include:
The AXI interface protocol can be used for:
Global clock signal
Global reset signal, active low
Write address ID (used to distinguish which write address group the address belongs to)
Burst size (the longest number of bytes per burst transmission)
Burst mode (FIXED, INCR, WRAP)
Storage type (the type of transfer required by the marking system)
Region identifier (identifies the logical interface used when the slave has multiple logical interfaces)
Write address valid signal (when valid, the address on AWADDR is valid)
Write slave ready signal (when valid, it means that the slave is ready to receive the address)
Data segment is valid (mark which 8-bit fields in the write data are valid)
last signal (when valid, it means that the current is the last data of burst transmission)
Write valid signal (when valid, the data on WDATA is valid)
Write ready signal (when valid, it means that the slave is ready to receive data)
Write response signal is valid
Write response ready (the host is ready to accept the write response signal)
Read address ID
Burst size (the number of bytes per burst transmission)
Burst type (FIXED, INCR, WRAP)
Type of protection
The read address is valid (when valid, the address on ARADDR is valid)
Write valid signal (when valid, it means that the slave is ready to receive the read address)
Read ID tag
When valid, it is the last one of the burst transmission
Read data valid signal
Host ready signal (indicated when valid)
When this signal is valid, the system exits the low-power mode
Exit low power mode response signal
Peripheral application clock signal
The reset signal can be reset asynchronously, but must be released synchronously . When resetting, the signal requirements are as follows:
The handshake signals include VALID and READY signals, and the transmission behavior only occurs when VALID and READY are valid at the same time. among them:
The sequence of VALID and READY has three situations:
In addition, it should be noted that the READY signal is allowed to wait for the VALID signal to be valid again, that is, even if the slave is ready, the READY signal may not be provided, and the READY signal is provided after the host sends the VALID signal. The corresponding VALID signal is not allowed to wait for the READY signal, that is, VALID is not allowed to wait for the READY signal to be pulled high and then pull it high, otherwise it is prone to deadlock.
During transmission, the sequence of channel transmission has the following regulations
In the following, some diagrams will be used to describe the dependencies. In the chart, the single arrow indicates that you can wait for valid and then reset, and the double arrow indicates that you must wait for valid and reset
The above figure shows the dependency of the read operation. ARREADY can wait for the ARVALID signal, and RVALID must wait for ARVALID and ARREADY to be valid at the same time (an address transfer occurs) to be valid
The only strong dependency in the write operation in AXI3 is the write response channel BVALID, which will be set only when the WVALID and WREADY signals are valid at the same time (data transmission is completed) and the WLAST signal is valid (the last data transmission of the burst transmission is completed) .
In AXI4, an additional dependency is defined, that is, BVALID must depend on the AWVALID, AWREADY, WVALID, and WREADY signals.
The AXI bus is a bus based on burst transmission. If the master wants to start a burst transmission, it needs to transmit an address and related control signals, and then the slave automatically calculates the address, but the address range of a burst transmission cannot exceed 4KB.
The burst length is the number of transmissions per burst transmission, the range is limited to 1~16 (AXI4 incremental mode 1~256) and cannot span the 4kb address space. Each burst transmission is not allowed to terminate early (you can close all data The field method makes a section of transmission data invalid, but the transmission behavior must be completed). The burst length of each transmission is AxLEN[3:0] + 1 (AXI incremental mode AxLEN[7:0] + 1)
For burst transmission in rewind mode, the burst length can only be 2, 4, 8, or 16.
The burst size is the number of bytes transmitted each time, which has a strong correlation with the address prediction of the burst transmission. The burst size of each time cannot exceed the width of the data channel; if the burst size is smaller than the width of the data channel, you need to specify which bits are valid. The burst size is 2AxSIZE[2:0].
AXI supports three burst types:
AXI4 can support different storage types, AxCACHE[3:0] is used to describe different storage types, as shown in the figure below
Normal Non-cacheable Non-bufferable
Normal Non-cacheable Bufferable
Write-through Read and Write-allocate
Write-back Read and Write-allocate
The AXI4 bus supports QoS, and the identifier AxQOS[3:0] indicates the priority of the service
The region identifier is used to specify the selected advanced logical interface type. When the identifier AxREGION[3:0] is used, it means that multiple logical interfaces share the physical interface
Authorization identifier AxPROT[2:0] is used to prevent illegal transmission
Each bit of WSTRB corresponds to 8 bits (1 byte) in the data, which is used to mark whether the corresponding byte in the data is valid. That is, when WSTRB[n] = 1, the WDATA[(8n)+7: (8n)] part of the mark data is valid.
When the transmitted data bit width is less than the xDATA bus bandwidth, it is narrow-band transmission, and the data bits used each time are different:
The figure above is a bitmap of the number of bits used for narrowband transmission using 8bit transmission under a 32-bit data signal under an address increment burst. The first transmission uses 0~7 bits, the second time uses 8~15 bits, increasing in order; in the fifth transmission, it returns to the beginning and uses 0~7 bits
When the transmission bit width exceeds 1 byte and the starting address is not an integer multiple of the data bus hardware bandwidth (byte unit), it is an unaligned transmission. When the transmission is not aligned, it is necessary to cooperate with the data strobe to invalidate certain bytes in the first transmission, so that the start address of the second burst transmission (automatically calculated by the slave) is an integer multiple of the burst size.
As shown in the figure, the burst size is 4 bytes. To align the transmission, the start address must be an integer multiple of 4. The starting address in the figure is 0x07, so it is non-aligned transmission. In the first transmission, the first 3 data are invalid fields, and the data strobe WSTRB can be used to invalidate the first 3 bytes.
The above figure shows the start of non-aligned transmission under narrowband transmission. The transmission bandwidth is 32bit, and each transmission uses 16bit. Because it is a narrowband transmission, the low byte and the high byte are alternately used each time. Now pay attention to the startup state. Since the startup address is 7 and the hardware bandwidth is 8bit, it must be started from address 0. Set the first 7 fields to be invalid. Then the next transmission starts from address 8, which satisfies unaligned transmission.
Response signals that respond to both read and write:
The meaning of the response signal is as follows:
There are two types of AXI slaves:
AxCACHE is used to specify the transmission characteristics, and the transmission characteristics are used to standardize how the transmission is performed in the system and how the system-level cache handles the transmission.
The memory characteristics include 4 bits, as shown below:
In addition, the AxLOCK and AxPROT signals still cannot be changed. At the same time, it should be noted that: AxCACHE=0, the sequence of a series of transmissions with the same AXI ID and to the same slave cannot be changed.
Define different memory types through the difference of ARCACHE and AWCACHE