AXI study notes-11. AXI bus structure 2. AXI interface timing 3. Data structure 4. Transmission characteristics

AXI study notes-11. AXI bus structure 2. AXI interface timing 3. Data structure 4. Transmission characteristics

1. AXI bus structure

The AXI bus consists of 5 channels:

Channel name

Channel function

Data flow

read address

Read address channel

Master -> Slave

read data

Read data channel (including data channel and read response channel)

Slave -> Host

write address

Write address channel

Master -> Slave

write data

Write data channel (including data channel and valid signal of write data with one byte per 8bit)

Master -> Slave

write response

Write response channel

Slave -> Host

1.1.AXI channel

The channel of the read operation is shown in the figure below

axi_read_channel.JPG

The channel of write operation is shown in the figure below

axi_write_channel.JPG

1.2.AXI system

Common standard AXI systems are shown in the figure below, which usually include:

  • AXI master: AXI communication master
  • AXI slave: AXI communication slave
  • AXI interconnect: AXI communication channel

axi_typical_system.JPG

The AXI interface protocol can be used for:

  • AXI master-AXI interconnect connection
  • AXI slave-AXI interconnect connection
  • AXI master-AXI slave connection

1.3.AXI interface

1.3.1. Global signal

Signal name

source

description

ACLK

system clock

Global clock signal

ARESTn

system reset

Global reset signal, active low

1.3.2. Write address channel

Signal name

source

description

AWID

master

Write address ID (used to distinguish which write address group the address belongs to)

AWADDR

master

Write address

AWLEN

master

Burst length

AWSIZE

master

Burst size (the longest number of bytes per burst transmission)

AWBURST

master

Burst mode (FIXED, INCR, WRAP)

AWCACHE

master

Storage type (the type of transfer required by the marking system)

AWPROT

master

Protection mode

AWQOS

master

QoS identifier

AWREGION

master

Region identifier (identifies the logical interface used when the slave has multiple logical interfaces)

AWUSER

master

User-defined signal

AWVALID

master

Write address valid signal (when valid, the address on AWADDR is valid)

AWREADY

master

Write slave ready signal (when valid, it means that the slave is ready to receive the address)

1.3.3. Write data channel

Signal name

source

description

WDATA

master

Write data

WSTRB

master

Data segment is valid (mark which 8-bit fields in the write data are valid)

WLAST

master

last signal (when valid, it means that the current is the last data of burst transmission)

WUSER

master

User-defined signal

WVALID

master

Write valid signal (when valid, the data on WDATA is valid)

WREADY

slave

Write ready signal (when valid, it means that the slave is ready to receive data)

1.3.4. Write response channel

Signal name

source

description

BID

slave

Response ID

BRESP

slave

Write response

BUSER

slave

User-defined signal

BVALID

slave

Write response signal is valid

BREADY

master

Write response ready (the host is ready to accept the write response signal)

1.3.5. Read address channel

Signal name

source

description

ARID

master

Read address ID

ARADDR

master

Read address

ARLEN

master

Burst length

ARSIZE

master

Burst size (the number of bytes per burst transmission)

ARBURST

master

Burst type (FIXED, INCR, WRAP)

ARCACHE

master

Storage type

ARPROT

master

Type of protection

ARQOS

master

QoS identifier

ARREGION

master

Area identifier

ARUSER

master

Custom

ARVALID

master

The read address is valid (when valid, the address on ARADDR is valid)

ARREADY

slave

Write valid signal (when valid, it means that the slave is ready to receive the read address)

1.3.6. Read data channel

Signal name

source

description

RID

slave

Read ID tag

RDATA

slave

Read data

RRESP

slave

Read response

RLAST

slave

When valid, it is the last one of the burst transmission

RUSER

slave

Custom

RVALID

slave

Read data valid signal

RREADY

master

Host ready signal (indicated when valid)

1.3.7. Low-power interface signals

Signal name

source

description

CSYSREQ

Clock controller

When this signal is valid, the system exits the low-power mode

CSYSACK

Peripheral device

Exit low power mode response signal

CACTIVE

Peripheral device

Peripheral application clock signal

2. AXI interface timing

2.1. Reset

The reset signal can be reset asynchronously, but must be released synchronously . When resetting, the signal requirements are as follows:

  • All VALID signals (ARVALID, AWVALID and WVALID) driven by the host must be pulled low
  • All VALID signals (RVALID and BVALID) driven by the slave must be pulled low
  • No other signals required

2.2. Basic transmission

2.2.1. Handshake signal

The handshake signals include VALID and READY signals, and the transmission behavior only occurs when VALID and READY are valid at the same time. among them:

  • The VALID signal indicates that the signal on the address/data/response signal bus is valid and is controlled by the transmission initiator
  • The READY signal indicates that the transmission receiver is ready to receive and is controlled by the transmission receiver

basic_handshake.png

The sequence of VALID and READY has three situations:

  • VALID is valid first, and the transmission is completed after READY is valid (Once VALID is valid, it cannot be cancelled before the transmission is completed)
  • READY is valid first, and the transmission is completed after waiting for VALID to be valid (READY can be withdrawn before VALID is valid)
  • VALID and READY are valid at the same time, and the transmission is completed immediately

In addition, it should be noted that the READY signal is allowed to wait for the VALID signal to be valid again, that is, even if the slave is ready, the READY signal may not be provided, and the READY signal is provided after the host sends the VALID signal. The corresponding VALID signal is not allowed to wait for the READY signal, that is, VALID is not allowed to wait for the READY signal to be pulled high and then pull it high, otherwise it is prone to deadlock.

2.2.1.1. Command channel handshake (read address, write address, write response)

  • Only when the address and other information is valid, the VALID is pulled high, and the VALID must be maintained until the transfer is completed (READY is set)
  • The default state of READY does not care, only pull READY up when ready to receive

2.2.1.2 Data channel handshake (write data and read address)

  • In the burst read and write mode, the VALID is pulled high only when the data information is valid, and the VALID must be maintained until the transfer is completed. Pull up the LAST signal when the last data of the burst transmission is sent
  • The default state of READY does not care, only pull READY up when ready to receive

2.2.2. Channel sequence

During transmission, the sequence of channel transmission has the following regulations

  • The write response channel transmission must be performed after the write operation is completed
  • The read data channel transmission must be carried out after the read address channel transmission
  • Must follow a series of state dependencies

In the following, some diagrams will be used to describe the dependencies. In the chart, the single arrow indicates that you can wait for valid and then reset, and the double arrow indicates that you must wait for valid and reset

2.2.2.1. Read operation sequence

read_depend.PNG

The above figure shows the dependency of the read operation. ARREADY can wait for the ARVALID signal, and RVALID must wait for ARVALID and ARREADY to be valid at the same time (an address transfer occurs) to be valid

2.2.2.2. Write operation sequence

write_depend.PNG

The only strong dependency in the write operation in AXI3 is the write response channel BVALID, which will be set only when the WVALID and WREADY signals are valid at the same time (data transmission is completed) and the WLAST signal is valid (the last data transmission of the burst transmission is completed) .

axi4_write_depend.PNG

In AXI4, an additional dependency is defined, that is, BVALID must depend on the AWVALID, AWREADY, WVALID, and WREADY signals.

3. Data structure

3.1. Address channel data structure

The AXI bus is a bus based on burst transmission. If the master wants to start a burst transmission, it needs to transmit an address and related control signals, and then the slave automatically calculates the address, but the address range of a burst transmission cannot exceed 4KB.

3.1.1. Burst transmission information

3.1.1.1. Burst Length (AxLEN)

The burst length is the number of transmissions per burst transmission, the range is limited to 1~16 (AXI4 incremental mode 1~256) and cannot span the 4kb address space. Each burst transmission is not allowed to terminate early (you can close all data The field method makes a section of transmission data invalid, but the transmission behavior must be completed). The burst length of each transmission is AxLEN[3:0] + 1 (AXI incremental mode AxLEN[7:0] + 1)

  • ARLEN[7:0]: Read the burst length interface of the address channel
  • AWLEN[7:0]: The burst length interface of the write address channel

For burst transmission in rewind mode, the burst length can only be 2, 4, 8, or 16.

3.1.1.2. Burst size (AxSIZE)

The burst size is the number of bytes transmitted each time, which has a strong correlation with the address prediction of the burst transmission. The burst size of each time cannot exceed the width of the data channel; if the burst size is smaller than the width of the data channel, you need to specify which bits are valid. The burst size is 2AxSIZE[2:0].

  • ARSIZE[2:0]: Read address channel burst size
  • AWSIZE[2:0]: write address channel burst size

3.1.1.3. Burst type (AxBURST)

AXI supports three burst types:

  • FIXED (AxBURST[1:0]=0b00): fixed burst mode, the address of each burst transmission is the same
  • INCR (AxBURST[1:0]=0b01): Incremental burst mode, the burst transmission address is incremented, and the increment is related to the burst size
  • WRAP (AxBURST[1:0]=0b10): Rewind burst mode, the burst transmission address can be overflowed and incremented, the burst length only supports 2, 4, 8, 16. The address space is divided into blocks of length [burst size * burst length], and the transmission address will not exceed the block where the starting address is located. Once the increase exceeds, it will return to the starting address of the block.

3.1.2. Storage Type (AxCACHE)

AXI4 can support different storage types, AxCACHE[3:0] is used to describe different storage types, as shown in the figure below

ARCACHE[3:0]

AWCACHE[3:0]

Memory type

0000

0000

Device Non-bufferable

0001

0001

Device Bufferable

0010

0010

Normal Non-cacheable Non-bufferable

0011

0011

Normal Non-cacheable Bufferable

1010

0110

Write-through No-allocate

1110 (0110)

0110

Write-through Read-allocate

1010

1110 (1010)

Write-through Write-allocate

1110

1110

Write-through Read and Write-allocate

1011

0111

Write-back No-allocate

1111

(0111) 0111

Write-back Read-allocate

1011

1111 (1011)

Write-back Write-allocate

1111

1111

Write-back Read and Write-allocate

3.1.3. Qos identifier (AxQOS)

The AXI4 bus supports QoS, and the identifier AxQOS[3:0] indicates the priority of the service

3.1.4. REGION Identifier (AxREGION)

The region identifier is used to specify the selected advanced logical interface type. When the identifier AxREGION[3:0] is used, it means that multiple logical interfaces share the physical interface

3.1.5. Authority identifier (AxPROT)

Authorization identifier AxPROT[2:0] is used to prevent illegal transmission

3.1.6. User-defined (AxUSER)

User-defined data

3.2. Data channel data structure

3.2.1. Data Strobe (WSTRB)

Each bit of WSTRB corresponds to 8 bits (1 byte) in the data, which is used to mark whether the corresponding byte in the data is valid. That is, when WSTRB[n] = 1, the WDATA[(8n)+7: (8n)] part of the mark data is valid.

3.2.2. Data (xDATA)

3.2.2.1. Narrow transfers

When the transmitted data bit width is less than the xDATA bus bandwidth, it is narrow-band transmission, and the data bits used each time are different:

  • Use the same segment of data signal line in a burst with a fixed address
  • In the burst of incremental address and packaging address, use different segments of signal lines

narrow.JPG

The figure above is a bitmap of the number of bits used for narrowband transmission using 8bit transmission under a 32-bit data signal under an address increment burst. The first transmission uses 0~7 bits, the second time uses 8~15 bits, increasing in order; in the fifth transmission, it returns to the beginning and uses 0~7 bits

3.2.2.2. Unaligned transfers

When the transmission bit width exceeds 1 byte and the starting address is not an integer multiple of the data bus hardware bandwidth (byte unit), it is an unaligned transmission. When the transmission is not aligned, it is necessary to cooperate with the data strobe to invalidate certain bytes in the first transmission, so that the start address of the second burst transmission (automatically calculated by the slave) is an integer multiple of the burst size.

Unaligned.JPG

As shown in the figure, the burst size is 4 bytes. To align the transmission, the start address must be an integer multiple of 4. The starting address in the figure is 0x07, so it is non-aligned transmission. In the first transmission, the first 3 data are invalid fields, and the data strobe WSTRB can be used to invalidate the first 3 bytes.

unaligned_narrow.PNG

The above figure shows the start of non-aligned transmission under narrowband transmission. The transmission bandwidth is 32bit, and each transmission uses 16bit. Because it is a narrowband transmission, the low byte and the high byte are alternately used each time. Now pay attention to the startup state. Since the startup address is 7 and the hardware bandwidth is 8bit, it must be started from address 0. Set the first 7 fields to be invalid. Then the next transmission starts from address 8, which satisfies unaligned transmission.

3.2.3. User-defined (*USER)

User-defined data

3.3. Response channel data structure

3.3.1. Response signal (*RESP)

Response signals that respond to both read and write:

  • BRESP[1:0] write response signal, after each burst transfer is completed
  • RRESP[1:0] Read response signal (located in the read data channel)

The meaning of the response signal is as follows:

  • OKAY (00): Normal access is correct/Privileged access fails/Privileged access is not supported
  • EXOKAY (01): The privileged access is successful
  • SLVERR (10): Slave error, transmission failed
  • DECERR (11): Interconnection decoding error, transmission failure

3.3.2. User-defined

User-defined data

4. Transmission characteristics

There are two types of AXI slaves:

  • Memory Slave: Need to support all transmission characteristics
  • Peripheral Slave: It only needs to support the specified operation, but it can guarantee the completion of all types of transmissions (not required to respond to non-specified operations correctly)

AxCACHE is used to specify the transmission characteristics, and the transmission characteristics are used to standardize how the transmission is performed in the system and how the system-level cache handles the transmission.

4.1. Memory characteristics

The memory characteristics include 4 bits, as shown below:

  • AxCACHE[0] (Bufferable): AxCACHE[0] indicates whether there is a buffer during transmission. When the position is 1, it indicates that there is a buffer on the transmission path (the time that the transaction can reach the final point can be delayed)
  • AxCACHE[1] (Modifiable): Mark whether the transmission can be modified/optimized. When it is set to 0, each transmission will not be changed. Specifically, the AxADDR, AxSIZE, AxLEN, AxBURST, AxLOCK and AxPROT signals will not Be modified (address, burst transmission information, transmission privacy information will not be modified). But AxCACHE[0], ID, and QoS may be modified. At the same time, a burst transmission with a burst length longer than 16 may be cut, but the transmission effect is guaranteed to be the same. When the position is 1, in addition to the above possible changes, in addition:
    • Multiple transmissions may be combined into one transmission, and one transmission may be divided into multiple transmissions
    • Read transmission may read more data on the slave side than the host request (more data is stored in the cache to optimize data access)
    • Write transfer may access to more than the address range requested by the host, use WSTRB properly to ensure that only the required address is covered

    In addition, the AxLOCK and AxPROT signals still cannot be changed. At the same time, it should be noted that: AxCACHE[0]=0, the sequence of a series of transmissions with the same AXI ID and to the same slave cannot be changed.

  • AxCACHE[2] (Read-allocate) and AxCACHE[3] (Write-allocate): Whether to check the cache before read and write operations to optimize transmission

4.2. Memory type

Define different memory types through the difference of ARCACHE and AWCACHE

mem_type.PNG

Reference: https://cloud.tencent.com/developer/article/1365277 AXI study notes-11. AXI bus structure 2. AXI interface timing 3. Data structure 4. Transmission characteristics-Cloud + community-Tencent Cloud