Delay constraints in FPGA timing constraints actual combat

Delay constraints in FPGA timing constraints actual combat

Delay constraint

  For the delay constraint, I believe that many students don't use it very much. The main reason is that they are not familiar with this constraint, and some are troublesome, because sometimes the time difference caused by the trace delay on the PCB is calculated. And without delay constraints, Vivado only prompts warning in the Timing Report, which will not cause timing errors. This will also make many students mistakenly believe that this constraint is dispensable.

  But in fact, this idea is wrong. For example, in many ADC designs, the edge of the output clock is exactly the center of the data. If we do not impose a delay constraint, Vivado will default the clock and data to be aligned.

  For input pins, first determine whether the capture clock is a master clock or a derived clock. If it is a master clock, use it directly set_input_delay. If it is a derived clock, create a virtual clock first, and then set the delay. For output pins, judge whether there is an output associated clock, if there is, use it directly set_output_delay, if not, you need to create a virtual clock.

  In this project, the capture clock of the input and output data pins is shown in the following table:

Pin

input Output

Capture clock

Clock type

Is there an associated clock

Do you need a virtual clock

rxd_pin

enter

clk_pin_p

Master clock

x

No

txd_pin

Output

clk_tx

x

no

Yes

lb_sel_pin

enter

clk_tx

Derived clock

x

Yes

led_pins[7:0]

Output

clk_tx

x

no

Yes

spi_mosi_pin

Output

spi_clk

x

Have

No

dac_*

Output

spi_clk

x

Have

No

  According to the above table, the delay constraints we created are as follows. The specific numbers in the actual project should be determined according to the timing relationship of upstream and downstream devices (which can be found in each device manual) and the PCB trace delay. To avoid the ambiguity of some constraints, we also add all the previous constraints.

# Master clock constraint
create_clock -period 25.000 -name clk2 [get_ports clk_in2]

# Derived clock constraints
create_generated_clock -name clk_samp -source [get_pins clk_gen_i0/clk_core_i0/clk_tx] -divide_by 32 [get_pins clk_gen_i0/BUFHCE_clk_samp_i0/O]
create_generated_clock -name spi_clk -source [get_pins dac_spi_i0/out_ddr_flop_spi_clk_i0/ODDR_inst/C] -divide_by 1 -invert [get_ports spi_clk_pin]
create_generated_clock -name clk_tx -source [get_pins clk_gen_i0/clk_core_i0/inst/mmcm_adv_inst/CLKIN1] [get_pins clk_gen_i0/clk_core_i0/inst/mmcm_adv_inst/CLKOUT1]
create_generated_clock -name clk_rx -source [get_pins clk_gen_i0/clk_core_i0/inst/mmcm_adv_inst/CLKIN1] [get_pins clk_gen_i0/clk_core_i0/inst/mmcm_adv_inst/CLKOUT0]

# Set asynchronous clock
set_clock_groups -asynchronous -group [get_clocks clk_samp] -group [get_clocks clk2]

# Delay constraint
create_clock -period 6.000 -name virtual_clock
set_input_delay -clock [get_clocks -of_objects [get_ports clk_pin_p]] 0.000 [get_ports rxd_pin]
set_input_delay -clock [get_clocks -of_objects [get_ports clk_pin_p]] -min -0.500 [get_ports rxd_pin]
set_input_delay -clock virtual_clock -max 0.000 [get_ports lb_sel_pin]
set_input_delay -clock virtual_clock -min -0.500 [get_ports lb_sel_pin]
set_output_delay -clock virtual_clock -max 0.000 [get_ports {txd_pin {led_pins[*]}}]
set_output_delay -clock virtual_clock -min -0.500 [get_ports {txd_pin {led_pins[*]}}]
set_output_delay -clock spi_clk -max 1.000 [get_ports {spi_mosi_pin dac_cs_n_pin dac_clr_n_pin}]
set_output_delay -clock spi_clk -min -1.000 [get_ports {spi_mosi_pin dac_cs_n_pin dac_clr_n_pin}]
Reference: https://cloud.tencent.com/developer/article/1653056 FPGA Timing Constraint Practical Chapter: Delay Constraints-Cloud + Community-Tencent Cloud