Why does the latch that everyone consistently avoids still exists in the FPGA? What are our misunderstandings about latches?

Why does the latch that everyone consistently avoids still exists in the FPGA? What are our misunderstandings about latches?

Preface

  In FPGA design, avoiding the use of latches is the consensus of almost all FPGA engineers. Xilinx and Altera also remind you in the manual to use latches with caution, unless you clearly know that you really need a latch to solve the problem. Moreover, most articles on the Internet have a misunderstanding about latches, which we will explain in detail later.

  In this article, we include the following:

  1. The principle and difference between latches, flip-flops and registers, why are latches bad?
  2. What kind of code will generate a latch?
  3. Why does the latch still exist in the FPGA?

The principle and difference between latches, flip-flops and registers, why are latches bad?

  The English of latch, flip-flop and register are: Latch, Flip-Flop, Register. Our translation of these three words is really intuitive, and you can guess their meaning from the names.

Latches

  1. What is a latch?

  The latch is used to store state information, which is to keep this state all the time. The latch is sensitive to the level of the pulse, that is, level trigger. Under the effective level, the latch is in the enabled state, and the output changes with the input. At this time, it does not latch the signal, just like a buffer When the latch is not enabled, the data is locked and the input signal has no effect. At this time, the output is always latched status information. Our common latches are SR latch, D latch, JK latch and so on.

  1. The working process of the latch

  Let's take the simplest D latch as an example to illustrate the working process of the latch. The D latch has 3 interfaces, which can also be considered as 4, because the output of two Qs and/overline{Q} Q are just Purely reverse relationship.

image

  Among them, D is the input signal. When E is high, the output Q is the input D; when E is low, Q keeps the last state when E is high, which is the latching process.

image

  1. Why is the latch bad?

  As can be seen from the above figure, the latch is not sensitive to glitches and it is easy to produce glitches on the signal; and there is no clock signal, so it is not easy to perform static timing analysis. It is for these two reasons that we try not to use latches when designing FPGAs.

  Of course, there is still a saying on the Internet that there are only LUT and FF resources in FPGA, and there is no ready-made Latch, so if you want to use Latch, you need more resources to build it out. But this view is wrong, and we will explain it specifically later.

trigger

  1. What is a trigger

  Flip-Flop (Flip-Flop, abbreviated as FF), also called bistable gate, also called bistable flip-flop. Translated as "forward and reverse" in Taiwan and Hong Kong, it is a storage component with two stable states, which can record binary digital signals "1" and "0".

  FPGA engineers are familiar with flip-flops. D flip-flops should be the most used element in our usual programming. In addition to D flip-flops, common flip-flops include T flip-flops, SR flip-flops, and JK flip-flops. The flip-flop is sensitive to the pulse edge, and its state only changes at the instant of the rising or falling edge of the clock pulse.

  1. The working process of the trigger

  We take the D flip-flop as an example to illustrate the working process of the flip-flop. The D flip-flop interface is as follows:

image

  The flip-flop only works on the edge of the clock, so even if there are glitches in the input signal, the output is relatively clean.

image

  Another thing to understand is that the smallest unit in FPGA is a gate circuit, which in turn constitutes a latch, and the latch constitutes a register.

register

  Some small storage areas used to store data are used to temporarily store data and calculation results involved in calculations. It is widely used in various digital systems and computers. In fact, a register is a commonly used sequential logic circuit, but this sequential logic circuit only contains a storage circuit. The storage circuit of the register is composed of latches or flip-flops. Because a latch or flip-flop can store a 1-bit binary number, N latches or flip-flops can form an N-bit register. The registers in the project are generally designed according to the number of bytes in the computer, so there are generally 8-bit registers, 16-bit registers, etc.

What kind of code will generate a latch?

In combinatorial logic , if the condition description is not complete, it will easily produce Latch:

  1. The else statement is missing in the if statement
  2. Not all circumstances are given in the case statement.

That is, the following situation:

always @ *
begin
    if(en==1)
        q <= d;
end
input [1:0]d;
always @ (d)
begin
    case(d)
    0: q0 <= 1'b1;
    1: q2 <= 1'b1;
    2: q2 <= 1'b1;
    3: q3 <= 1'b1;
    default: q4 <= 1'b1;
end

  This premise is that in the combinational circuit, in the if statement of the sequential circuit, there is no else in time, and the Latch will not be synthesized.

  Where do the above two writing methods easily appear? The most common is the state machine. I have seen many FPGA engineers writing state machines without all the variables in the case statement.

Why does the latch still exist in the FPGA?

  We said earlier that there is a saying on the Internet that there are only LUT and FF resources in FPGA, and there is no ready-made Latch, so if you want to use Latch, you need more resources to get it out. This statement is wrong, because in Xilinx FPGAs, devices before the 6 series have Latch; in 6 series and 7 series FPGAs, 50% of the storage elements in a slice can be configured as Latch or Flip- Flop, the other half can only be configured as Flip-Flop. For example, in a 7 series FPGA, there are 8 Flip-Flops in a slice. If it is configured as Latch, the other 4 Flip-Flops of the slice cannot be used. This does cause a waste of resources.

image

In UltraScale FPGA, all storage elements can be configured as Flip-Flop and Latch.

image

We use the following code to illustrate the result of Flip-Flop and Latch implementation in Ultrascale FPGA.

Flip-Flop code:

module FF_top(
 input clk,
 input [3:0] data_i,
 input data_ie,//enable
 output reg [3:0] o_latch
    );

always @ (posedge clk)
begin
    if(data_ie)
        o_latch <= data_i;
end  

endmodule

Latch code:

module latch_top(
 input [7:0] data_i,
 input data_ie,//enable
 output reg [7:0] o_latch
    );

always @ * 
begin
    if(data_ie)
        o_latch[3:0] <= data_i[3:0];
end  


endmodule

The Schematic and Device implemented by Flip-Flop are as follows:

image

The Schematic and Device after the Latch is implemented are as follows:

image

It can be seen that when using Flip-Flop, storage element is integrated into FDRE, which is a trigger; when using Latch circuit, storage element is integrated into LDCE.

  Therefore, the statement that there is no Latch in FPGA is wrong in Xilinx FPGA.

The last question, since there are so many problems with Latch, why should it be retained in FPGA?

  1. First of all, because of the flexibility of the FPGA circuit, retaining the Latch does not affect the resources of the FPGA, because the storage element can be directly configured as Flip-Flop.
  2. The second is that some functions must use Latch. For example, many processor interfaces require a Latch to cache data or addresses.

  The last point to be explained is: Although latches are not used much in FPGAs, they are very common in CPUs because latches are much faster than Flip-Flop.

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Reference: https://cloud.tencent.com/developer/article/1652221 Why does the latch that everyone consistently avoids still exists in the FPGA? What are our misunderstandings about latches? -Cloud + Community-Tencent Cloud