The correct way to open FPGA reset

The correct way to open FPGA reset

This article refers to Xilinx White Paper: Get Smart About Reset: Think Local, Not Global

Before reading this article, recall the usual reset methods we usually use:

  1. First of all, it must be reset after power-on, otherwise there will be no initial value during simulation;

  2. It's better to have a reset button, you can reset it globally by pressing the reset button during debugging;

  3. It may be a synchronous reset or an asynchronous reset. Different engineers may have different solutions.

But if you read Xilinx's White Paper carefully, you will have a new understanding of reset. We summarize the contents of the White Paper into the following 4 questions:

  1. Do I need to reset?

  2. Synchronous reset or asynchronous reset?

  3. High reset or low reset?

  4. Global reset or local reset? how to use?

1. Do I need to reset?

  Seeing this problem, many students may be a little confused, how could it not be necessary to reset? In fact, Xilinx FPGA will have a GSR (Global Set/Reset) signal when the system is powered on and configured. This signal has the following characteristics:

  • Pre-wired
  • High fanout
  • reliable

This signal can initialize all cells, including all Flip-Flop and BRAM.

If we use the reset signal generated by ourselves in the program, we can only reset Flip-Flop.

  This GSR signal can be STARTUPdirectly called by instantiation in the program , but Xilinx does not recommend it.

The main reason is that FPGA will put high-fan-out signals like system reset on high-speed routing resources, which is faster than using GSR, and it is easier to perform timing analysis.

  Although there is GSR, this does not mean to avoid the use of reset signal, the following two situations must be reset:

  • Modules with feedback, such as filters and state machines like IIR, need to be reset when the state runs off
  • Registers that need to be reset during application

  This depends on the specific application. Many of our company's registers need to be reset frequently during the debugging process. Such a reset is necessary.

Therefore, the need to reset depends entirely on the design. Here is a bit more, the timing closure is the same, mainly depends on the design, not the constraints.

2. Synchronous reset or asynchronous reset?

  In HDL, if rst is not included in the sensitive list, it will be integrated into a synchronous reset:

always @ (posedge clk)
begin
    if(rst)
        ...
end

If rst is included in the sensitive list, it will be integrated into an asynchronous reset:

always @ (posedge clk or posedge rst)
begin
    ...
end

The benefits of synchronous reset are self-evident, which is conducive to timing analysis, reducing the probability of metastability and avoiding glitches.

Disadvantages of synchronization signal:

  • The duration of the active level of the reset signal must be greater than the clock period, otherwise the clock may not be able to reset
  • Cannot reset when there is no clock

  Many students will also say that synchronous reset will require additional resources, but for Xilinx FPGAs, there is no such problem. The specific reasons will be discussed later.

For asynchronous reset, the advantage is the opposite of synchronous reset: the pulse width is not limited, and it can be reset without a clock.

The disadvantage is that asynchronous circuits are easy to cause metastable state and produce glitches, which are not conducive to timing analysis, and the reset time of different flip-flops may be different. In the figure below, the FF that receives the reset signal pulled low at time A can release the reset state at the next rising edge of the clock, but the FF that receives the reset signal pulled low at the time C can release the reset at the next rising edge of the clock status.

According to the White Paper, there is a 99.99% probability that this situation will not happen, but if you happen to encounter this phenomenon once, then you are 0.01%.

Let's give an example to illustrate synchronous reset and asynchronous reset, FPGA is V7, the code is as follows:

module rst_demo(
 input clk,
 input rst1,
 input rst2,
 input in1,
 input in2,
 output reg out1,
 output reg out2);

 always @ (posedge clk)
 begin
    if(rst1)
        out1 <= 1'b0;
    else
        out1 <= in1;
 end

 always @ (posedge clk or posedge rst2)
 begin
    if(rst2)
        out2 <= 1'b0;
    else
        out2 <= in2;
 end

 endmodule

The schematic after synthesis is as follows:

It can be seen that both synchronous reset and asynchronous reset occupy a Storage Element. We mentioned in a previous article that Storage Element can be configured as Latch. Similarly, it can also be configured as FDRE and FDCE, and it is also in the 7Series manual. It is not mentioned whether it will take up more resources when configured as FDRE or FDCE (for example, in the 7Series FPGA, there are 8 Storage Elements in a Slice. If one of them is configured as Latch, then 4 Storage Elements cannot be used. Used), so in Xilinx FPGA, there is no difference between synchronous reset and asynchronous reset in terms of resource occupation.

3. High reset or low reset?

  The resets on many processors are low resets, which also causes many students to get used to using low resets when using reset signals. But from what we said in the previous section, whether it is a synchronous reset or an asynchronous reset, the reset signal is high and effective. If a low reset is used, an inverter needs to be added.

  If we receive a low-effective reset signal sent by other processors, we'd better reverse the polarity of the reset signal in the top-level module. In this way, the inverter can be placed in the IO Logic without occupying the logic resources and internal logic of the FPGA. Cabling resources.

  One more thing to add here, if you use Zynq and Microblaze, the Reset module defaults to a low reset, and we can manually set it to a high reset.

4. Global reset or local reset? how to use?

  Our common practice for reset is to connect each FF in the system to a reset signal, but this results in a high fan-out of the reset signal, which can easily lead to timing violations. And the resources occupied by global reset are much higher than we thought:

  • Wiring resource occupation
  • The wiring space of other networks is reduced accordingly
  • May reduce system performance
  • Increase wiring time
  • Logical resource occupation
  • Occupy FF as a dedicated reset circuit
  • If the reset signal is also controlled by other signals, it will cause the gate circuit to be added before the FF input
  • Will increase the size of the entire design
  • Increased logical resources will affect system performance
  • Increase placement and routing time
  • Global reset will not use an efficient structure like SRL16E
  • SRL16E can be regarded as 16 FF in LUT
  • These Virtual FFs do not support reset
  • Increase design size and reduce system performance
  • Increase placement and routing time

Therefore, Xilinx recommends to use partial reset as much as possible. We also mentioned earlier that there are some problems with synchronous reset and asynchronous reset. Is there a way to combine the advantages of synchronous reset and asynchronous reset? Of course there is, that is, asynchronous reset and synchronous release. This method can combine the two and learn from each other. As shown in the figure below, the so-called asynchronous reset means that the input reset signal is still asynchronous, which ensures that the reset signal can take effect; while synchronous release means that when the reset signal is released, the output sys_rstdoes not change immediately and is delayed by FF A clock cycle is added, so that the reset and the clock are synchronized.

The Verilog code in the figure is as follows:

module rst_demo(
 input clk, 
 input rst_async, 
 (* keep = "true" *)
 output reg rst_module1 = 0,
 (* keep = "true" *)
 output reg rst_module2 = 0
    );

reg sys_rst;
reg rst_r;

always @(posedge clk or posedge rst_async) begin
    if (rst_async) begin
        rst_r <= 1'b1;
    end
    else begin
        rst_r <= 1'b0;
    end
end

always @(posedge clk or posedge rst_async) begin
    if (rst_async) begin
        sys_rst <= 1'b1;
    end
    else begin
        sys_rst <= rst_r;
    end
end

always @ (posedge clk) begin
    rst_module1 <= sys_rst;
    rst_module2 <= sys_rst;
end

endmodule

The schematic after synthesis is as follows:

The output of the asynchronous reset module sys_rstpasses through n D flip-flops and is output to n modules as the module's reset signal.

summary

  When using the reset signal, consider whether this register needs to be reset during operation. If you only need to reset once after power-on, you only need to write the initial value when defining it, without using other reset signals; in Xilinx Use a highly effective reset signal as much as possible in the FPGA, adopt an asynchronous reset synchronous release method, and localize the reset signal to avoid using a high fan-out global reset.

Reference: https://cloud.tencent.com/developer/article/1653044 The correct way to open FPGA reset-Cloud + Community-Tencent Cloud